Subject: RE: [vhdl-200x] Re: TBV2: Associative arrays proposal submitted
From: Stephen Bailey (SBailey@model.com)
Date: Mon Apr 28 2003 - 08:41:27 PDT
I did say typically.
If you want to get into reasons why, it is because busses typically have
multiple drivers. Resolution of multiply driven integers busses is not well
supported (by synthesis tools and even in simulation, you would need to
model the disconnection of a driver). Therefore, the busses themselves are
typically modeled as std_logic_vectors. Of course, I would also agree that
most memory models do a to_integer translation of the address bus to an
integer value to serve as an index into an array that models the memory
contents. And, that is my point: If everyone does it, shouldn't the
language facilitate this type of modeling to reduce the amount of code
required?
-Steve Bailey
> -----Original Message-----
> From: Colin Marquardt [mailto:c.marquardt@alcatel.de]
> Sent: Monday, April 28, 2003 9:31 AM
> To: Stephen Bailey
> Cc: 'Jim Lewis'; vhdl-200x
> Subject: Re: [vhdl-200x] Re: TBV2: Associative arrays
> proposal submitted
>
>
> Stephen Bailey <SBailey@Model.com> writes:
>
> > The address bus is typically modeled as a bit vector and
> not as an integer
> > value.
>
> Really? Not around here at least. I have nothing against supporting
> both vectors and integers of course.
>
> Cheers,
> Colin
>
> --
> > . . . I along with many other hardware engineers can already
> > see the day when your boss doesn't hand you a Word or PDF
> > document for the specifications of a design, but instead will
> > hand you a VHDL or Verilog testbench file.
> Wow. The future is bright. In 2003, I'm lucky to get 3 bullet
> items on a powerpoint slide :) [Mike Treseler in comp.arch.fpga]
>
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