[vhdl-200x] Re: TBV2: Associative arrays proposal submitted

Subject: [vhdl-200x] Re: TBV2: Associative arrays proposal submitted
From: Jim Lewis (Jim@synthworks.com)
Date: Sun Apr 27 2003 - 20:48:42 PDT

Why address in bit/std_logic? To address in integer
all that is required is a call to to_integer?
So the to_integer would be built into the call.
What happens when address = "X" for write and
for read? Write invalidate all entries?
Read, readback an "X"?


Stephen Bailey wrote:
>>Is an associative array the same as the sparse array (TBV12)?
>>I think a sparse array was intended for creating space
>>on demand for modeling something like a RAM. Sounds
>>like associative array is the same thing.
> Associative arrays could be used to model sparse arrays. However, sparse arrays are more specific. They are used specifically for
> modeling large memories efficiently when only a small percentage of the memory addresses are used in any given simulation.
> To easily model sparse memories, associative arrays would need to support:
> 1. A bit (std_logic) vector as an index expression. (The memory address.)
> 2. Support constraining the index according to the memory size.
> I had requested that the proposal ensure that both of these be covered (permitted).
> There may also be efficiency of implementation considerations that might determine that sparse arrays should either have their own
> syntax or that a standard "generic" associative array subtype be defined to be used for sparse array/memory modeling. Either of
> these would then be what implementations key on to kick in any relevant optimizations.
> BTW, it would also be good to define load and dump operations for associative/sparse arrays.
> -Steve Bailey

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