Subject: Re: [vhdl-200x] CFA: Priorities
From: Stephen Bailey (Stephen.Bailey@synopsys.com)
Date: Tue Mar 11 2003 - 08:22:54 PST
Below is Gabe Moretti's comments which bounced due to his posting from a
non-subscribed address. (Gabe, I have added your comcast email address to the
post-as-well list so this should not happen in the future.)
-Steve Bailey
> Since Evan in discussing the Assertions priority has specifically asked me
> to address his point, I will take the opportunity to answer and question
> another point.
> First the assertions questions. I do not differentiate between Accellera
> assertions and other assertions. I think that VHDL needs a more powerful
> set of assertions, and I assume that the first task of the WG is to
> determine what is needed. I am a bit surprised that we even found it
> necessary to divide logical assertion from temporal assertions. Formal
> verification techniques have been proven to work and there exist EDA tools
> today that do a good job at it. Temporal assertions are useful and we
> understand how to implement it. I find no reasons to separate the two.
> Sop, my vote for assertions is a vote for both item 8 and item 27.
> I have a question with respect to item 4. If we finish and vote on VHPI do
> we not get much or possibly all of the capabilities that item 4 would
> develop? Are we creating more work for ourselves than what we need to do?
> Gabe
> ----- Original Message -----
> From: "Stephen Bailey" <Stephen.Bailey@synopsys.com>
> To: <vhdl-200x@server.eda.org>
> Sent: Tuesday, March 11, 2003 12:59 AM
> Subject: [vhdl-200x] CFA: Priorities
>
>
> > Attached is an update on the current priorities list. Today (10 Mar 03)
> was the
> > suspense date for collecting this information. However, if you have not
> had an
> > opportunity to provide this data to me yet, please do so ASAP. I will
> continue
> > to collect the information through thursday night for presentation to the
> VHDL
> > 200x Steering Committee (all technical team leaders and myself) on Friday.
> >
> > NOTE: In addition to updating the priorities based on additional inputs,
> I have
> > sorted the data to make it easier to identify the top priorities as
> expressed by
> > the membership of this WG.
> >
> > If you are new to the group and have not seen the presentation which
> contains
> > the base list of requests for language enhancements, please send me an
> email and
> > I will send you that presentation.
> >
> > -----------------------------------------------------------------
> > Stephen Bailey
> > Staff Corporate Applications Engineer, VHDL Simulation
> > Synopsys Inc.
> > sbailey@synopsys.com
> > 303-775-1655 (voice/mobile)
> > 650-584-4893 (corporate voice mail)
> > Read Verification Avenue:
> > http://www.synopsys.com/va
> > -----------------------------------------------------------------
> >
>
>
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