Re: [vhdl-200x], vital issues

Subject: Re: [vhdl-200x], vital issues
From: Paul J. Menchini (
Date: Fri Mar 07 2003 - 11:48:22 PST

'nother bouncer from David Bishop <>. I think
it's the last one, as I think we have the list straight now....



> Jayaram Bhasker wrote:
>> Peter:
>> Exactly. This would involve describing the correspondence between Verilog and
>> VHDL ports as part of the standard.
>> The rules that I have seen so far is:
>> 1. Ports match by name
>> 2. Case sensitive (vhdl port names are case-sensitive) - so user should use the
>> same case in VHDL as it appears in the verilog module

> How about "VHDL port names will be assumed to match to lower case unless
> escaped with a "\". Example "Clock" will map to "clock", but "\Clock\" will map
> to "Clock" in Verilog.

>> 3. Number of ports must match.
>> 4. VHDL port types can only be std_(u)logic, std_(u)logic_vector.

> Very important. No resolution functions in Verilog.

>> 5. Generics - hmmm, i havent tried/used these - but we could come up with a reasonble definition.

> Generics work great, but you can only pass ones of type integer to Verilog
> parameters.

> 6) architecture of a Verilog module statment (when use in a VHDL configuration)
> should be called "verilog".

> As an example, one of the packages I have posted for the floating point packages
> is a Verilog co-simulation package:


> It's been tested in Modeltech, but it should work in others.

> --
> David W. Bishop

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