Subject: RE: [vhdl-200x], vital issues
From: Jayaram Bhasker (JBhasker@eSilicon.com)
Date: Fri Mar 07 2003 - 10:48:36 PST
Peter:
Exactly. This would involve describing the correspondence between Verilog and
VHDL ports as part of the standard.
The rules that I have seen so far is:
1. Ports match by name
2. Case sensitive (vhdl port names are case-sensitive) - so user should use the
same case in VHDL as it appears in the verilog module
3. Number of ports must match.
4. VHDL port types can only be std_(u)logic, std_(u)logic_vector.
5. Generics - hmmm, i havent tried/used these - but we could come up with a reasonble definition.
- bhasker
------
J. Bhasker, eSilicon Corp
1605 N. Cedar Crest Blvd, Ste 615, Allentown, PA 18104
jbhasker@esilicon.com, 610.439.6831, 610.770.9634(fax)
-----Original Message-----
From: Peter Ashenden [mailto:peter@ashenden.com.au]
Sent: Friday, March 07, 2003 11:07 AM
To: Jayaram Bhasker; 'Jim Lewis'; vhdl-200x@server.eda.org
Subject: RE: [vhdl-200x], vital issues
Bhasker,
> With two of the simulators that I use, as long as the verilog
> models are compiled into work,
> I have no problem linking them in. So the question is, can I
> compile verilog models into a
> vhdl library called VLIB and use "use VLIB.all;" to link the
> models during elaboration? Jim, I guess
> this is what you are looking for, right?
This initially made me think of foreign architectures. The difference,
however, is that you don't want to have to write a VHDL entity
declaration corresponding to the Verilog module. Instead, you want VHDL
to be able to understand the Verilog module's interface. That would
mean defining a correspondence between Verilog port names, types and
directions on the one hand and VHDL port nameds, types and directions on
the other hand. Am I understanding this correctly?
Cheers,
PA
-- Dr. Peter J. Ashenden peter@ashenden.com.au Ashenden Designs Pty. Ltd. www.ashenden.com.au PO Box 640 Ph: +61 8 8339 7532 Stirling, SA 5152 Fax: +61 8 8339 2616 Australia Mobile: +61 414 70 9106
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