RE: [P1800] P1800 SystemVerilog Ballot Draft (4.0) is ready

Dave, you're right.
Section 2 is supposed to be literals (which is marked as section 3).

Stu, can you please look into this ASAP? We may need to fix the ballot 
draft for this.

thanks,

--- Johny.





"Rich, Dave" <Dave_Rich@mentorg.com> 
02/16/2005 09:22 AM

To
Johny Srouji/Austin/IBM@IBMUS, <ieee1800@eda.org>
cc
<stuart@sutherland-hdl.com>
Subject
RE: [P1800] P1800 SystemVerilog Ballot Draft (4.0) is ready






BTW, are my eyes failing me, or is this draft missing section 2? (or maybe 
both).
 
I think section 3 was supposed to be section 2.
 
Dave
 
 
 
 

From: owner-ieee1800@eda.org [mailto:owner-ieee1800@eda.org] On Behalf Of 
Johny Srouji
Sent: Monday, February 14, 2005 8:48 AM
To: ieee1800@eda.org
Subject: [P1800] P1800 SystemVerilog Ballot Draft (4.0) is ready
 

Hi All, 

Please note that P1800 SystemVerilog Ballot draft is ready and was 
uploaded (thanks to Dennis) to our web site under: 
http://grouper.ieee.org/groups/1800/private/P1800-draft4_SystemVerilog_LRM.pdf 


This version is a clean draft (no colored text, change bars, etc) and it 
will be our draft for Ballot. 

I would like to use this opportunity to thank you all for the hard work in 
enabling this, and to our technical editor, Stu Sutherland, who has been 
making excellent progress and follow-up on all of our drafts. 

Enjoy, 

--- Johny.