[sv-ac] Sampled value functions

Hi all,

 

There are several limitations / gray places in the LRM concerning the
sampled values functions.

 

1. Why has the following limitation been introduced (17.7.3 Sampled
value functions)?

 

When these functions are used in an assertion, the clocking event
argument of the functions, if specified, shall be identical to the
clocking event of the expression in the assertion. In the case of
multiclock assertions, the appropriate clocking event for the expression
where the function is used is applied to the function.

 

2. It is not stated explicitly whether the sampled value functions can
be nested. E.g., is $past($rose(a)) legal?

 

3. There is no explicit specification whether the sampled value
functions may be used in non-clocked always blocks, e.g., always_comb a
<= $past(b,,posedge clk).

 

4. May the clocking event be different from the inferred clocking event?
E.g.,

 

always @(posedge clk) a = $past(b,, negedge clk1);

 

5. It is written that the sampled value functions may be written inside
the procedural code only. Why? E.g., this is illegal:

 

assign a = $rose(b, posedge clk)

 

Thanks,

Dmitry