RE: [sv-ac] Sampled value functions

Hi Doron,

just a comment regarding the first item, polease see below.

ed
 

> -----Original Message-----
> From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On 
> Behalf Of Doron Bustan
> Sent: Tuesday, May 09, 2006 3:35 PM
> To: Korchemny, Dmitry
> Cc: sv-ac@eda.org
> Subject: Re: [sv-ac] Sampled value functions
> 
> My take on it
> 
> >  
> >
> > 1. Why has the following limitation been introduced (17.7.3 Sampled 
> > value functions)?
> >
> >  
> >
> > When these functions are used in an assertion, the clocking event 
> > argument of the functions, if specified, shall be identical to the 
> > clocking event of the expression in the assertion. In the case of 
> > multiclock assertions, the appropriate clocking event for the 
> > expression where the function is used is applied to the function.
> >
> >  
> >
> 
> I am not sure that it is clear when an evaluation attempt 
> should occur. 
> For example
> 
> always @(c1) begin
> if (a) assert property (@(c2) b);
> end
> 
> Now, suppose that c2 is 3 times faster than c1, and that in the first 
> occurrence of c1, "a" holds.
> should there be 3 attempts of "b"? or just one ?
> Should "a" be evaluated according to c2, and c1 should be ignored?
> 

I think that the point from Dmitry's message refers to the system
functions, while you meant the use of a different clock in a property
embedded in an always block. 

With regards to that, Ithink that the interpretation is that the normal
clock flow would still keep c2 as the clock of the property and the
condition a would be (syntactically) extracted and inserted in the
assertion. The effective code after extraction would look like this:

always @(c1) begin
end

assert property (@(c2) a |-> b);