RE: [sv-ac] Sampled value functions

Hi Doron,

Please, see my comments below.

Thanks,
Dmitry

-----Original Message-----
From: Doron Bustan [mailto:dbustan@freescale.com] 
Sent: Tuesday, May 09, 2006 10:35 PM
To: Korchemny, Dmitry
Cc: sv-ac@eda.org
Subject: Re: [sv-ac] Sampled value functions

My take on it

>  
>
> 1. Why has the following limitation been introduced (17.7.3 Sampled 
> value functions)?
>
>  
>
> When these functions are used in an assertion, the clocking event 
> argument of the functions, if specified, shall be identical to the 
> clocking event of the expression in the assertion. In the case of 
> multiclock assertions, the appropriate clocking event for the 
> expression where the function is used is applied to the function.
>
>  
>

I am not sure that it is clear when an evaluation attempt should occur. 
For example

always @(c1) begin
if (a) assert property (@(c2) b);
end

Now, suppose that c2 is 3 times faster than c1, and that in the first 
occurrence of c1, "a" holds.
should there be 3 attempts of "b"? or just one ?
Should "a" be evaluated according to c2, and c1 should be ignored?

[Korchemny, Dmitry] 
It is a matter of definition. Since we don't allow clock change within
the overlapping implication, we have to define it as a standalone
assertion
assert property (@(c2) a |-> b);

> 2. It is not stated explicitly whether the sampled value functions can

> be nested. E.g., is $past($rose(a)) legal?
>
>  
>

I think it should be allowed.

> 3. There is no explicit specification whether the sampled value 
> functions may be used in non-clocked always blocks, e.g., always_comb 
> a <= $past(b,,posedge clk).
>
>  
>
> 4. May the clocking event be different from the inferred clocking 
> event? E.g.,
>
>  
>
> always @(posedge clk) a = $past(b,, negedge clk1);
>
I think this should be legal, but we need to specified the exact 
semantics (similar to multi clocking).

something like:

This $past operator is nonoverlapping and synchronizes between the 
clocks of the
$past function and the clock inferred from the context. For a 
$past(sig0, 1 ,@c1)
that is poisoned in the context of another clock c2, the sampling of  
sig0 is
understood to be from at the point, which occurs at a tick of c2, to the

nearest strictly anterior
tick of c1. For a $past(sig0, n ,@c1) that is poisoned in the context of

another clock c2, the sampling of  sig0 
is understood to be n-1 ticks of c1 before the sampling of $past(sig0, 1

,@c1).


[Korchemny, Dmitry] My understanding is that $past(a,1,1'b1,@(posedge
clk)) is always (in any context) equivalent to:

type(a) pa;
always @(posedge clk) pa <= a;

(I am using posedge in order to avoid the complications with @(clk), but
it is the same idea).

>  
>
> 5. It is written that the sampled value functions may be written 
> inside the procedural code only. Why? E.g., this is illegal:
>
>  
>
> assign a = $rose(b, posedge clk)
>

do we want the following code to be legal:

module cnt(input clk, input [3:0] bus, input load, output  [3:0] res);
 
assign res = ($past(load,1,   @(posedge clk)) ?  $past(bus,1, @(posedge 
clk)) : $past(reg ,1, @(posedge clk)) + 1;

endmodule

???

If not, what prevents it ?

[Korchemny, Dmitry] Why not?

Doron