[sv-ac] Clocks in assrtion

Hi,

 

SVA imposes several restrictions on the assertion clocks, which are
sometimes painful. Could somebody explain what the reason of these
restrictions is (I marked my questions with (?)):

 

Section 17.14 Clock resolution

 

b) The following rules apply within a clocking block:

 

1) No explicit clocking event is allowed in any property or sequence
declaration within the clocking block. (?)

2) Multiclocked sequences and properties are not allowed within the
clocking block. (?)

3) If a named sequence or property that is declared outside the clocking
block is instantiated within the clocking block, the instance must be
singly clocked and its clocking event must be identical to that of the
clocking block. (?)

 

c) A contextually inferred clocking event from a procedural block
supersedes a default clocking event.

The contextually inferred clocking event is treated as though it had
been written as the leading

clocking event of any concurrent assertion statement to which the
inferred clock applies. The maximal

property of such a concurrent assertion statement must be singly clocked
(?), and the clocking

event, if specified otherwise, must be identical to the contextually
inferred clocking event. (?)

 

Thanks,

Dmitry