Subject: Re: [sv-ac] Example showing reporting of variables in action block.
From: Surrendra Dudani (Surrendra.Dudani@synopsys.com)
Date: Tue Aug 26 2003 - 13:31:16 PDT
Hi Adam,
The reason for not including assert statement was primarily due to the
existence of action blocks. An action block can include any statement, so
in effect, clocking domains would also allow any statement. This creates a
new challenge to define semantics of Verilog statements under a clocking
domain, and enlarges the scope of clocking domain's functionality beyond
what was intended.
The main use of a clocking domain for defining properties and sequences is
to allow a grouping of definitions under a common clock, so that the clock
doesn't need to be repeated, and the related definitions live in a group
together.
Surrendra
At 02:19 PM 8/26/2003 -0500, you wrote:
>Hi Surrendra;
>
> >Assert or Cover statements are not allowed in clocking domains.You can
> only have >definitions , but not statements in clocking domain. So, this
> limits to the definition
> >of a property or a sequence.
>
>So is this an erratta, or desired? Given no LRM on this area it is hard
>to discern.
>My first thought about only definitions is what benefit one obtains by placing
>an assertion definition into a clocking domain.
>
>Jay and Arturo show value of having the assert/cover statement in the domain.
>
> >However, one can use clocking domain definition to access the sampled
> values, such as
>
>This IMHO is not a good solution because one has to create this little
>block basically
>after writing the assertion/property. You have to:
>1. Remember to create the clocking domain.
>2. List *ALL* the signals in your message/action block (hope you don't
>forget one.)
>3. Reference the signals in the clocking domain block (hope you don't
>forget to
> do this too.)
>
>This is a lot, and very easy to get wrong...
>
>clocking my_clock @(posedge clk);
> input a,b,c;
>endclocking
>
>always @(my_clock)
> assert property (a => b ##1 c)
> else $error("C (%0d) did not follow b after a.\n", myclock.c);
>
>I would hope that assert and cover statements were accidently omitted.
>
> Thanks.
>
> Adam Krolnik
> Verification Mgr.
> LSI Logic Corp.
> Plano TX. 75074
>
**********************************************
Surrendra A. Dudani
Synopsys, Inc.
377 Simarano Drive, Suite 300
Marlboro, MA 01752
Tel: 508-263-8072
Fax: 508-263-8123
email: Surrendra.Dudani@synopsys.com
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