Subject: RE: [sv-ac] Example showing reporting of variables in action block.
From: Jay Lawrence (lawrence@cadence.com)
Date: Tue Aug 26 2003 - 11:13:19 PDT
There was a bunch of discussion around eliminating all the redundant
syntax (redeclaring the inputs etc. but I don't recall the "implicit
declarations" Arturo refers to below being decided on, and it certainly
isn't in the current LRM. However, I think it would make a great cleanup
topic, especially if we could get assertion sampling semantics to be
identical to that of the clocking domain.
I would even go so far as to have assertions in sequential code
implicitly declare a clocking domain in which they live so we could
really unify these 2 concepts.
Jay
===================================
Jay Lawrence
Senior Architect
Functional Verification
Cadence Design Systems, Inc.
(978) 262-6294
lawrence@cadence.com
===================================
> -----Original Message-----
> From: Arturo Salz [mailto:Arturo.Salz@synopsys.com]
> Sent: Tuesday, August 26, 2003 2:09 PM
> To: Adam Krolnik; Jay Lawrence
> Cc: sv-ac@eda.org
> Subject: Re: [sv-ac] Example showing reporting of variables
> in action block.
>
>
> Adam,
>
> Since the signals within the clocking domain (a,b,c) are
> referenced by the
> property, they are implicitly declared as inputs to the
> clocking domain.
> So there's no need to declare them individually. The two examples you
> wrote below should be equivalent. You are, however, right that the LRM
> does not describe this.
>
> Arturo
>
> ----- Original Message -----
> From: "Adam Krolnik" <krolnik@lsil.com>
> To: "Jay Lawrence" <lawrence@cadence.com>
> Cc: <sv-ac@eda.org>
> Sent: Tuesday, August 26, 2003 10:53 AM
> Subject: Re: [sv-ac] Example showing reporting of variables
> in action block.
>
>
>
>
> Hi Jay;
>
> >If assertions and the pass/fail statements are placed in a clocking
> >domain then the sampling is controlled explicitly by the
> clocking domain
> >sensitivity, and both the assertion and the pass/fail see
> the sampled
> >values.
>
> You know, I read the clocking domain section earlier today.
> There is no
> description or example discussing how this works. There is
> *only* a reference
> through the BNF in the section.
>
> Is it this straightforward?
>
> clocking @(posedge clk);
>
> assert property
> (a => b ##1 c)
> else
> $error("C (%0d) did not follow b after a.\n", c);
>
> endclocking
>
> Somehow, I figure the answer is no. From reading the section,
> I think it needs to
> be:
>
> clocking @(posedge clk);
> default input #1step; // Specify get sampled values.
> input a, b, c; // List all signals used below **1
>
> assert property
> (a => b ##1 c)
> else
> $error("C (%0d) did not follow b after a.\n", c);
>
> endclocking
>
> Is it required to list all signals used in assertions as
> inputs? This will be
> a source of 'oh I forgot', or 'hmmm, I must've missed that
> signal.' It would
> be safer if all referenced signals were included automatically...
>
> Also, the BNF shows an optional clocking domain name. This is
> good as one
> will probably have assertions/properties spread through the
> RTL code, not in
> one place...
>
> THanks.
>
> Adam Krolnik
> Verification Mgr.
> LSI Logic Corp.
> Plano TX. 75074
>
>
>
>
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