Subject: Re: [sv-ac] Example showing reporting of variables in action block.
From: Adam Krolnik (krolnik@lsil.com)
Date: Tue Aug 26 2003 - 12:08:13 PDT
Hi Jay;
Hmmm,
>There was a bunch of discussion around eliminating all the redundant
>syntax (redeclaring the inputs etc. but I don't recall the "implicit
>declarations" Arturo refers to below being decided on, and it certainly
>isn't in the current LRM. However, I think it would make a great cleanup
May I suggest a sv-bc item to clarify how this all works?
>topic, especially if we could get assertion sampling semantics to be
>identical to that of the clocking domain.
>I would even go so far as to have assertions in sequential code
>implicitly declare a clocking domain in which they live so we could
>really unify these 2 concepts.
If you would IMplicitly declare a clocking domain for procedural assertions,
they why not IMplicitly declare a clocking domain for concurrent assertions?
It seems funny to write, concurrent assertions will need an explicit clocking
domain to produce correct error messages, but procedural assertions implicitly
have a clocking domain...
Or, by sequential do you mean the non immediate (assert property) versions?
I would be in favor of an IMplicit clocking domain - less to type, remember,
safer, etc.
Two additional comments.
1. Its too bad that one can't define a default clocking domain
and then reference that when creating another clocking domain.
E.g.
default clocking gclk @(posedge clk)
...
endclocking
clocking default; // Use previously defined default clocking.
...
endclocking
I wouldn't have to replicate the @(posedge clk) with each clocking domain.
2. If default clocking domains were visible from a child scope, then modules
without an explicit clock, could make use of a parent's clocking domain.
I.e. for a module without a clock, one could write assertions referencing
upward to get the parent's clock.
Thanks.
Adam Krolnik
Verification Mgr.
LSI Logic Corp.
Plano TX. 75074
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