Subject: Re: [sv-ac] Example showing reporting of variables in action block.
From: Adam Krolnik (krolnik@lsil.com)
Date: Tue Aug 26 2003 - 12:19:05 PDT
Hi Surrendra;
>Assert or Cover statements are not allowed in clocking domains.You can only have
>definitions , but not statements in clocking domain. So, this limits to the definition
>of a property or a sequence.
So is this an erratta, or desired? Given no LRM on this area it is hard to discern.
My first thought about only definitions is what benefit one obtains by placing
an assertion definition into a clocking domain.
Jay and Arturo show value of having the assert/cover statement in the domain.
>However, one can use clocking domain definition to access the sampled values, such as
This IMHO is not a good solution because one has to create this little block basically
after writing the assertion/property. You have to:
1. Remember to create the clocking domain.
2. List *ALL* the signals in your message/action block (hope you don't forget one.)
3. Reference the signals in the clocking domain block (hope you don't forget to
do this too.)
This is a lot, and very easy to get wrong...
clocking my_clock @(posedge clk);
input a,b,c;
endclocking
always @(my_clock)
assert property (a => b ##1 c)
else $error("C (%0d) did not follow b after a.\n", myclock.c);
I would hope that assert and cover statements were accidently omitted.
Thanks.
Adam Krolnik
Verification Mgr.
LSI Logic Corp.
Plano TX. 75074
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