Subject: [sv-ac] Proposal for action blocks using sampled variables.
From: Adam Krolnik (krolnik@lsil.com)
Date: Fri Sep 05 2003 - 07:19:04 PDT
Good morning all;
I would like to propose the modification of action block semantics to use sampled
values of variables. Justifications follow:
1. As it is written in the LRM,
"Assertions are primarily used to validate the behavior of a design."
I believe the current operation of action blocks making use of variable values
different than what is used by the sequences and properties of the assertion
contributes to confusion and ease of producing the wrong result. These problems
will degrade the acceptance and overall use of assertions to improve design
processes.
2. A secondary purpose of assertions is to be able to generate stimulus based on
the success or failure of sequences and properties. This purpose is where people
find the ability to use current variable value relevant.
The problem with the action block's use of variable values is that it best supports
the secondary purpose. Thus I propose that we remove the secondary purpose of assertions
and move it somewhere else. With the secondary purpose removed, we should support
the primary purpose be allowing the action blocks to use the sample values of
referenced variables.
For the secondary purpose of generating stimulus, there are proposals to wait or
detect the success of a property/sequence. With this ability in place, one can
write additional verilog code to perform any desired action, thus removing the
burden from the assert statement.
People have expressed desires to prevent assertion statements from modifying the
design state. By allowing the wait() and @() constructs to accept properties or
sequences as their arguments, we provide for this desire (that assertions are only
for inspection, not reaction) and for the desire to react to specific sequences.
Finally, the draft proposal:
1. The action block should use sampled values for all explicitly referenced variables
in the code block. Any tasks or functions called that reference variables not
passed in through their arguments will use the current variable values.
2. Through the use of .ended, .failed, method calls on sequence or property types
it is possible to use the statement wait() or @() and control the actions of
common verilog code to react to stimulus.
With these methods, one can summarize their use as follows:
o Assert/cover - Use to report unacceptable operation in verilog codes (assert),
or to record acceptable operations in verilog codes (cover)
o wait(seq_prop.ended)
wait(seq_prop.failed)
@(seq_prop.ended)
@(seq_prop.failed) - Use to react to operations in verilog code and provide
additional stimulus or other operations.
I submit this for commentary and if satisfactory will writeup the full proposal with
LRM changes and replacements.
Thanks.
Adam Krolnik
Verification Mgr.
LSI Logic Corp.
Plano TX. 75074
Co-Author "Assertion Based Design"
This archive was generated by hypermail 2b28 : Fri Sep 05 2003 - 07:19:43 PDT