Subject: Re: [sv-ac] Re: R58c - access to past values ... with enable
From: Joseph Lu (Juin-Yeu.Lu@sun.com)
Date: Thu Sep 19 2002 - 16:26:01 PDT
>Date: Thu, 19 Sep 2002 15:08:27 -0700
>From: Bassam Tabbara <bassam@novas.com>
>X-Accept-Language: en
>MIME-Version: 1.0
>To: Adam Krolnik <krolnik@lsil.com>
>CC: Cindy Eisner <EISNER@il.ibm.com>, sv-ac@eda.org
>Subject: [sv-ac] Re: R58c - access to past values ... with enable
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>X-OriginalArrivalTime: 19 Sep 2002 22:08:27.0227 (UTC) FILETIME=[146AE2B0:01C26029]
>
>Adam,
>
>Thx for the example, 2 things.
>
>1) I think you are making a statement about -sampling-, so as I said earlier, I do not see why this is limited
>to "prev", you are giving one example using that construct, if
>there is an enhancement to sampling I'm sure there are other examples of this symptom.
>2) In the example, I'm afraid I don't see why doing:
>
>.... prev(expr, 1)@(posedge (clk) && clk_en) does not do what you want to do for:
I am wondering if Verilog allow you to do @(posedge (clk) && clk_en). It is an event expression.
The only operator to compose two event expressions is or.
--Joseph
>
>always @(posedge clk) (2)
> if (clk_en) p_expr <= expr;
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