Re: [sv-ac] Re: R58c - access to past values ... with enable

Subject: Re: [sv-ac] Re: R58c - access to past values ... with enable
From: Bassam Tabbara (bassam@novas.com)
Date: Fri Sep 20 2002 - 11:20:19 PDT

Who's talking about Verilog ? prev ??? Yes as I said this is an event expression so in a pseudo assertion description
sync the_clk: posedge(clk) && clk_en

prev(expr, 1)@@(the_clk) in some way/shape or form (DAS/OVA/PSL...)

-Bassam.

Joseph Lu wrote:

>Date: Thu, 19 Sep 2002 15:08:27 -0700
>From: Bassam Tabbara <bassam@novas.com>
>X-Accept-Language: en
>MIME-Version: 1.0
>To: Adam Krolnik <krolnik@lsil.com>
>CC: Cindy Eisner <EISNER@il.ibm.com>, sv-ac@eda.org
>Subject: [sv-ac] Re: R58c - access to past values ... with enable
>Content-Transfer-Encoding: 7bit
>X-OriginalArrivalTime: 19 Sep 2002 22:08:27.0227 (UTC) FILETIME=[146AE2B0:01C26029]
>

>Adam,
>
>Thx for the example, 2 things.
>
>1) I think you are making a statement about -sampling-, so as I said earlier, I do not see why this is limited
>to "prev", you are giving one example using that construct, if
>there is an enhancement to sampling I'm sure there are other examples of this symptom.
>2) In the example, I'm afraid I don't see why doing:
>
>.... prev(expr, 1)@(posedge (clk) && clk_en) does not do what you want to do for:

I am wondering if Verilog allow you to do @(posedge (clk) && clk_en). It is an event expression.
The only operator to compose two event expressions is or.

--Joseph

>
>always @(posedge clk)                     (2)
>    if (clk_en)  p_expr <= expr;

-- 
Dr. Bassam Tabbara
Technical Manager, R&D

Novas Software, Inc.
bassam@novas.com
(408) 467-7893
 

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