Subject: [sv-ac] Re: R58c - access to past values ... with enable
From: Adam Krolnik (krolnik@lsil.com)
Date: Thu Sep 19 2002 - 15:31:17 PDT
Hi Bassam;
How do you evaluate this @() expression? Is it consistent with verilog?
>prev(expr, 1)@(posedge (clk) && clk_en)
Let me expand some code to show what is happening.
always @(posedge clk)
begin
areg <= next_areg;
...
end
always @(areg or ...)
begin
nxt_en = F(areg, breg, etc.)
d = q + 1;
...
end
always @(posedge clk)
begin
if (nxt_en) q <= d;
...
end
cycle 1 2 3 4 5 6
__ __ __ __ __ __
clk | |__| |__| |__| |__| |__|
____________ _______________
nxt_en |_____|
d 1 2 3 4 5 6
Q 1 2 2 4 5
#2p_expr 1 1 3 4 5
The signal nxt_en is deasserted in cycle 3. What cycle does it
affect the update of Q? Cycle 3 or Cycle 4?
Verilog has it effect the value at cycle 4 but not allowing the update.
The reason I place the enable inside the previous expression is because
you need to use the previous value of the enable to decide if you
want to get the previous value of the expression..
It is an excercise to the reader on how to obtain the previous value
of a register (when last enabled)
always @(posedge clk)
if (enable) q <= d;
Hint:
$prev(d, 1, enable) === prev(enable) ? prev(d) : prev(prev(d, 1,
enable))
Adam Krolnik
Verification Mgr.
LSI Logic Corp.
Plano TX. 75074
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