Subject: Re: [sv-ac] Zero/Non-zero delay model (is it same as synchronous vs asynchronous)
From: Alain Raynaud (alain@tensilica.com)
Date: Thu Sep 19 2002 - 15:42:44 PDT
The way I see it at Tensilica, we mostly write "functional assertions":
properties that should hold true at the end of a cycle. We don't care
about propagation delays, don't want to see messages from a simulator
reporting transient failures, and don't want to ask a formal model
checker to report possible glitches as if they were functional bugs.
So I would say 90% of our properties would be happy to use the
synchronous/zero-delay model. Now, there might be a few areas with
external bus protocols and sophisticated memory interfaces, where one
would like to specify assertions that contain absolute delays and
therefore care about propagation time.
Does this correlate with an implicit syntax where the assertion is
written as:
" a # b " : means "a" followed at the next cycle by "b" - zero-delay
" a #10ns b " : means "a" followed after an absolute time by "b" -
non-zero delay
Can a language support both modes?
Rajeev Ranjan wrote:
> I would seek feedback from the end users/managers like Adam Krolnik
> and Harry Foster who have had extensive experience with assertion
> methodology as to a) whether the "delay independent" specification
> could limit any of their assertion b) if not, what training/guidelines
>
> they used to ensure that the designers/assertion writers do not make
> such mistakes.
Alain Raynaud
Tensilica, Inc.
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