Subject: Re: Performance issues
From: Steve Casselman (sc@vcc.com)
Date: Fri Apr 04 2003 - 09:47:31 PST
OK. So what in your opinion is the reason that Verilog simulation are
thought of as running faster than VHDL? Are there simulators that have a
common simulation core where VHDL and Verilog simulations run at the same
speed?
Steve
> I have been involved with the VITAL standard and it's implementation for
> several years, and from my experience I can confidently say this: There is
> nothing in the standard that prevents VITAL being accelerated to the same
> levels as Verilog gates.
>
> -ajay
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