Subject: Re: Performance issues
From: Ajayharsh Varikat (ajay@cadence.com)
Date: Thu Apr 03 2003 - 22:25:10 PST
>> I think the last message before we went off to separate groups was about
>> "why is VHDL simulation performance less than Verilog performance?" One
>> theory was more time and optimization has been put into Verilog simulation
>> than VHDL and the other was there is something intrinsically bad about Vital
>> that hampers simulation performance.
I have been involved with the VITAL standard and it's implementation for
several years, and from my experience I can confidently say this: There is
nothing in the standard that prevents VITAL being accelerated to the same
levels as Verilog gates.
-ajay
This archive was generated by hypermail 2b28 : Thu Apr 03 2003 - 22:25:27 PST