Subject: Performance issues
From: Steve Casselman (sc@vcc.com)
Date: Thu Apr 03 2003 - 09:43:05 PST
I think the last message before we went off to separate groups was about
"why is VHDL simulation performance less than Verilog performance?" One
theory was more time and optimization has been put into Verilog simulation
than VHDL and the other was there is something intrinsically bad about Vital
that hampers simulation performance.
Any thoughts?
Steve
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