Subject: Fixed link to template: [vhdl-200x-mp] Re: Bi-directional signal flow
From: Jim Lewis (Jim@SynthWorks.com)
Date: Wed Apr 30 2003 - 17:06:52 PDT
Bidirectional assignment is on the list.
It is a matter of formalizing the request, submitting
an analysis, voting, and resolving the issue.
We need a volunteer or two to address this issue.
Anyone interested in volunteering? (hint)
This is issue MP-001. The proposal template is at:
http://www.eda-twiki.org/vhdl-200x/vhdl-200x-mp/proposals/proposal_template.txt
Cheers,
Jim
Steve Casselman wrote:
> Verilog has many constructs like this. It allows Verilog to model almost
> anything you need to model and design an ASIC. I believe that Verilog is the
> language most ASIC designers use because of this (and performance issues).
> What would it take to have VHDL cover the same turff as Verilog in this
> respect?
>
> Steve
> ----- Original Message -----
> From: "Kevin Cameron x3251" <Kevin.Cameron@nsc.com>
> To: <vhdl-200x-mp@server.eda.org>
> Sent: Wednesday, April 30, 2003 9:56 AM
> Subject: [vhdl-200x-mp] Re: Bi-directional signal flow
>
>
>
>>>From owner-vhdl-200x-dta@eda.org Wed Apr 30 06:50:10 2003
>>>
>>>Kevin,
>>>
>>>
>>>>Is this the right group for tackling bi-directional signal flow (for
>>>>modeling transmission gates etc.)?
>>>
>>>No, I'd say that the right group is Modeling and Productivity
>>>(vhdl-200x-mp).
>>>
>>>Paul
>>
>>A friend of mine has been bugging me for a while to fix this aspect of
>>VHDL for him, is anyone else interested?
>>
>>The extensions would allow users to create digital models for transmission
>>gates and other bi-directional devices.
>>
>>Kev.
>>
>
>
>
>
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