Subject: Re: [vhdl-200x-mp] Re: Bi-directional signal flow
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Mon May 05 2003 - 09:56:29 PDT
> From Jim@synthworks.com Sat May 3 19:52:33 2003
>
> Hi Rick,
> You sound a little frustrated. We have an issue
> list based on the DVCon documents (posted on
> vhdl-200x home page). This issue is already
> on the list.
>
> > What else should I do to promote my cause?
> Perhaps flush out some detail of what you envision
> for the implementation.
>
> For example, when I first started thinking of this
> I thought of a bidirectional operator that
> attaches two bidirectional ports:
>
> A <=> B ;
>
> However, David Bishop showed me some interesting
> things he would like to be able to do for pass-gate
> multiplexers:
>
> bidir_mux : process (Sel, A, B, C)
> begin
> case sel is
> when "00" => A <=> B ;
> when "01" => A <=> C ;
> when "10" => B <=> C ;
> when others =>
> end case ;
> end process ;
>
>
> If we do this, do we need to be able to do
> concurrent assignments:
> A <=> B when S = '1' else C ;
>
>
> Do we allow the following or do the expressions
> have to resolve to signals?
> A <=> B and C ;
>
>
> Your request includes, switches, resistors, and
> transmission gates. I think the above may address
> switches and transmission gates, how do we do resistors?
I think that approach is equivalent to a "programmable short
circuit" i.e. for "A <=> B" you assume all the drivers of A
and B are resolved together and the result is applied to A and
B. Seems like useful functionality but adding strength reduction
is rather difficult, also I don't see why I couldn't do both
"A <=> B" and "A <=> C" at the same time which implies (to me)
that you would need another operator to undo the short ("<!>" ?),
and then you have a problem with "B <!> C" after "A <=> B" and
"A <=> C" (which implicitly shorts B & C).
I don't think you can get the desired functionality with a single
operator, and the "sticky" behavior is probably hard to debug
or do static analysis on.
Regards,
Kev.
> At minimum the above needs to be made some sense
> of an integrated into the MP-001 proposal.
>
> Cheers,
> Jim
>
>
>
>
>
> Munden Rick wrote:
> > Jim,
> >
> > OK, I have submitted the proposal (for the third time). What else
> > should I do to promote my cause?
> >
> > Rick
> >
> > Jim Lewis wrote:
> >
> >> Bidirectional assignment is on the list.
> >> It is a matter of formalizing the request, submitting
> >> an analysis, voting, and resolving the issue.
> >>
> >> We need a volunteer or two to address this issue.
> >> Anyone interested in volunteering? (hint)
> >>
> >> This is issue MP-001. The proposal template is at:
> >>
> >> http://www.eda-twiki.org/vhdl-200x/proposals/proposal_template.txt
> >>
> >> Cheers,
> >> Jim
> >>
> >>
> >>
> >> Steve Casselman wrote:
> >>
> >>> Verilog has many constructs like this. It allows Verilog to model almost
> >>> anything you need to model and design an ASIC. I believe that Verilog
> >>> is the
> >>> language most ASIC designers use because of this (and performance
> >>> issues).
> >>> What would it take to have VHDL cover the same turff as Verilog in this
> >>> respect?
> >>>
> >>> Steve
> >>> ----- Original Message ----- From: "Kevin Cameron x3251"
> >>> <Kevin.Cameron@nsc.com>
> >>> To: <vhdl-200x-mp@server.eda.org>
> >>> Sent: Wednesday, April 30, 2003 9:56 AM
> >>> Subject: [vhdl-200x-mp] Re: Bi-directional signal flow
> >>>
> >>>
> >>>
> >>>>> From owner-vhdl-200x-dta@eda.org Wed Apr 30 06:50:10 2003
> >>>>>
> >>>>> Kevin,
> >>>>>
> >>>>>
> >>>>>> Is this the right group for tackling bi-directional signal flow (for
> >>>>>> modeling transmission gates etc.)?
> >>>>>
> >>>>>
> >>>>>
> >>>>> No, I'd say that the right group is Modeling and Productivity
> >>>>> (vhdl-200x-mp).
> >>>>>
> >>>>> Paul
> >>>>
> >>>>
> >>>>
> >>>> A friend of mine has been bugging me for a while to fix this aspect of
> >>>> VHDL for him, is anyone else interested?
> >>>>
> >>>> The extensions would allow users to create digital models for
> >>>> transmission
> >>>> gates and other bi-directional devices.
> >>>>
> >>>> Kev.
> >>>>
> >>>
> >>>
> >>>
> >>>
> >>
> >
> >
> >
>
>
>
>
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