Subject: [vhdl-200x-mp] status & procedural things for proposals
From: Jim Lewis (Jim@SynthWorks.com)
Date: Sat May 03 2003 - 19:36:18 PDT
Currently the list of requested features for MP is
still in rough form of the conference documents.
Links to these documents are at: http://www.eda-twiki.org/vhdl-200x.
I have an action to sort through these and post the list
to the proposals.html document. I will complete this
by the end of May. It will be in the same format that
I did for the FT page.
So for the time being, to procede, if there is an
issue in the MP area of the conference documents in
which you are interested, please submit a proposal
to the reflector. If you can, please flush out
your proposal with examples of how you want to use
the feature. For reference, please see the proposals in the
fast track (http://www.eda-twiki.org/vhdl-200x/vhdl-200x-ft),
testbench and verification (http://www.eda-twiki.org/vhdl-200x/vhdl-200x-ft),
and std_logic working groups for examples.
Thanks,
Jim
Munden Rick wrote:
> Jim,
>
> OK, I have submitted the proposal (for the third time). What else
> should I do to promote my cause?
>
> Rick
>
> Jim Lewis wrote:
>
>> Bidirectional assignment is on the list.
>> It is a matter of formalizing the request, submitting
>> an analysis, voting, and resolving the issue.
>>
>> We need a volunteer or two to address this issue.
>> Anyone interested in volunteering? (hint)
>>
>> This is issue MP-001. The proposal template is at:
>>
>> http://www.eda-twiki.org/vhdl-200x/proposals/proposal_template.txt
>>
>> Cheers,
>> Jim
>>
>>
>>
>> Steve Casselman wrote:
>>
>>> Verilog has many constructs like this. It allows Verilog to model almost
>>> anything you need to model and design an ASIC. I believe that Verilog
>>> is the
>>> language most ASIC designers use because of this (and performance
>>> issues).
>>> What would it take to have VHDL cover the same turff as Verilog in this
>>> respect?
>>>
>>> Steve
>>> ----- Original Message ----- From: "Kevin Cameron x3251"
>>> <Kevin.Cameron@nsc.com>
>>> To: <vhdl-200x-mp@server.eda.org>
>>> Sent: Wednesday, April 30, 2003 9:56 AM
>>> Subject: [vhdl-200x-mp] Re: Bi-directional signal flow
>>>
>>>
>>>
>>>>> From owner-vhdl-200x-dta@eda.org Wed Apr 30 06:50:10 2003
>>>>>
>>>>> Kevin,
>>>>>
>>>>>
>>>>>> Is this the right group for tackling bi-directional signal flow (for
>>>>>> modeling transmission gates etc.)?
>>>>>
>>>>>
>>>>>
>>>>> No, I'd say that the right group is Modeling and Productivity
>>>>> (vhdl-200x-mp).
>>>>>
>>>>> Paul
>>>>
>>>>
>>>>
>>>> A friend of mine has been bugging me for a while to fix this aspect of
>>>> VHDL for him, is anyone else interested?
>>>>
>>>> The extensions would allow users to create digital models for
>>>> transmission
>>>> gates and other bi-directional devices.
>>>>
>>>> Kev.
>>>>
>>>
>>>
>>>
>>>
>>
>
>
>
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