RE: [vhdl-200x-ft] IP Protection Syntax & VHDL

For those of you who may have missed, forgotten, or intentionally
blocked it from your mind; a rather long-winded explanation of the
lexical vs. syntactic description can be found on this reflector on
5/19/2004 from me ('lawrence@cadence.com').

For the sake of brevity I won't repost it here. Let me know directly if
you want it and I will forward ....

Jay

===================================
Jay Lawrence
Senior Architect
Functional Verification
Cadence Design Systems, Inc.
(978) 262-6294
lawrence@cadence.com
===================================

>-----Original Message-----
>From: owner-vhdl-200x-ft@eda.org
>[mailto:owner-vhdl-200x-ft@eda.org] On Behalf Of Bailey, Stephen
>Sent: Friday, December 24, 2004 12:40 PM
>To: vhdl-200x-ft@eda.org
>Subject: RE: [vhdl-200x-ft] IP Protection Syntax & VHDL
>
>Jim,
>
>The protected regions need to be lexical and not semantic for the
>greatest level of flexibility in what gets encrypted vs. not encrypted.
>Therefore, the protect-begin-end structure won't work as it is
>semantic.
>
>The syntax of the lexically specified protected areas is not the most
>important part of the proposal, by which I mean that if
>someone can come
>up with something better than `protect or whatever is proposed, please
>forward that.
>
>-Steve Bailey
>
>> Hi,
>> I was just browsing the IP encryption proposal.
>> I noticed that its syntax is not exactly VHDL in that it uses
>> `protect as a keyword.
>>
>> I have two conflicting perspectives on this:
>> 1) Leave it alone. It seems here there would be a big
>> advantage for tool vendors to have compatibility between the
>> VHDL and Verilog protection approaches.
>> From a user perspective, even if we VHDLize the syntax, I
>> don't think it would result in less typing.
>> Note, this argument has most meaning if the protection syntax
>> for both VHDL and Verilog are identical.
>>
>> 2) Make it VHDL like. There seems to be two distinct
>> regions, a setup/declarative section and a code to be
>> protected region. This would seem to suggest that the syntax
>> would be more like:
>> protect
>> -- declarations
>> begin -- protected region
>> -- protected code
>> end protect ;
>>
>> I don't really think this (2) is a good thing. Once you
>> start considering how do we create the pragma values in
>> VHDL it starts getting interesting. Particularly
>> considering that some pragmas are used more than once in
>> the same region.
>>
>>
>> While my inclination is to leave it alone, I think everyone
>> should be aware that the syntax is not quite VHDL and be
>> ready to ballot positively. If you do have an objection to
>> the current syntax, make sure to propose an alternative.
>>
>> Cheers,
>> Jim
>> --
>> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> Jim Lewis
>> Director of Training mailto:Jim@SynthWorks.com
>> SynthWorks Design Inc. http://www.SynthWorks.com
>> 1-503-590-4787
>>
>> Expert VHDL Training for Hardware Design and Verification
>> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>>
>>
>
>
Received on Mon Jan 3 12:45:27 2005