[vhdl-200x-ft] IP Protection Syntax & VHDL

Hi,
I was just browsing the IP encryption proposal.
I noticed that its syntax is not exactly VHDL in
that it uses `protect as a keyword.

I have two conflicting perspectives on this:
1) Leave it alone. It seems here there would be
a big advantage for tool vendors to have compatibility
between the VHDL and Verilog protection approaches.
 From a user perspective, even if we VHDLize the syntax,
I don't think it would result in less typing.
Note, this argument has most meaning if the protection
syntax for both VHDL and Verilog are identical.

2) Make it VHDL like. There seems to be two distinct
regions, a setup/declarative section and a code to be
protected region. This would seem to suggest that the
syntax would be more like:
   protect
     -- declarations
   begin -- protected region
     -- protected code
   end protect ;

   I don't really think this (2) is a good thing. Once you
   start considering how do we create the pragma values in
   VHDL it starts getting interesting. Particularly
   considering that some pragmas are used more than once in
   the same region.

While my inclination is to leave it alone, I think
everyone should be aware that the syntax is not quite
VHDL and be ready to ballot positively. If you do have
an objection to the current syntax, make sure to propose
an alternative.

Cheers,
Jim

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Jim Lewis
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SynthWorks Design Inc.           http://www.SynthWorks.com
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