[vhdl-200x-ft] FT10A Syntax Change Proposals

Hi,
I have received a proposals to change the syntax of FT10A.

The current syntax is:
   nnary_expression ::=
     {logical if condition ,} logical

   A few examples using the current syntax:
     Y <= A if B if C, D, E ;
     Signal X : integer := 7 if GEN_VAL = 1, 15 ;
     Y <= A if Asel=’1’, B if Bsel=’1’, C if Csel=’1’, D if Dsel=’1’, E ;
     Y <= A if Asel, B if Bsel, C if Csel, D if Dsel, E ; -- with boolean equiv
     port ( data : std_logic_vector(
              ( 7 if word_size <= 8, 15 if word_size <= 16, 31) downto 0);

Alternative 1: Use parens to surround the condition:
   nnary_expression ::=
     {logical if ( condition ) } logical

    Same examples using this proposed syntax:
     Y <= A if (B if (C) D) E ;
     Signal X : integer := 7 if (GEN_VAL = 1) 15 ;
     Y <= A if (Asel=’1’) B if (Bsel=’1’) C if (Csel=’1’) D if (Dsel=’1’) E ;
     Y <= A if (Asel) B if (Bsel) C if (Csel) D if (Dsel) E ; -- with boolean equiv
     port ( data : std_logic_vector(
              ( 7 if (word_size <= 8) 15 if (word_size <= 16) 31)) downto 0);

Alternative 2: Use parens to surround the condition:
   nnary_expression ::=
     {logical if condition else } logical

    Same examples using this proposed syntax:
     Y <= A if B if C else D else E ;
     Signal X : integer := 7 if GEN_VAL = 1 else 15 ;
     Y <= A if Asel=’1’ else B if Bsel=’1’ else C if Csel=’1’ else D if Dsel=’1’ else E ;
     Y <= A if Asel else B if Bsel else C if Csel else D if Dsel else E ; -- with boolean equiv
     port ( data : std_logic_vector(
              ( 7 if word_size <= 8 else 15 if word_size <= 16 else 31) downto 0);

Comments appreciated.

Cheers,
Jim

-- 
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Jim Lewis
Director of Training             mailto:Jim@SynthWorks.com
SynthWorks Design Inc.           http://www.SynthWorks.com
1-503-590-4787
Expert VHDL Training for Hardware Design and Verification
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