[vhdl-200x-ft] Boolean Equivalence, FT18

Hi,
Currently FT18 proposes one way of creating some sort
boolean equivalence between boolean and bit as well as
between boolean and std_ulogic.

FT18 is implemented in two parts.
1) A function is used to convert from bit or
    std_ulogic to boolean at the highest outermost
    level of a condition.

    Hence this step allows the following:
    signal CS1, CS2 : std_logic ;
    ...
    if CS1 and CS2 then ...

2) Overloaded logic operators are provided that allow
    boolean and bit to be used together and return bit, as
    well as, overloaded logic operators that allow boolean
    and std_ulogic to be used together and return std_ulogic.

    Hence this step allows the following:
    signal SEL, CS1, CS2 : std_logic ;
    signal Addr : std_logic_vector(7 downto 0) ;
    ...
    if CS1 and CS2 and Addr = X"AA" then ...

    Also due to this overloading, I can do:

    SEL <= CS1 and CS2 and Addr = X"AA" ;

One thing that cannot be done is:
    -- SEL <= Addr = X"AA" ; -- error, result is boolean

    Note although this is strange, it is not uncommon. For
    example with numeric_std:
    signal A, Y : unsigned(7 downto 0) ;

    Y <= A + 1 ; -- legal, unsigned + integer = unsigned
    -- Y <= 1 ; -- error, literal is integer

Another is:
    signal BoolSel : boolean ;

    -- BoolSel <= CS1 and CS2 and Addr = X"AA" ; -- error result is std_ulogic

--------------------------------------------------------
Proposal 1:
Add to the current proposal, FT18, for boolean equivalence
an additional set of comparison operators that
return either std_ulogic or bit (such as eq, ne, gt, ge,
lt, le). Overloading the current operators would lead to
ambiguous expressions.

In conjunction with the boolean equivalence proposal, the
new operators could replace the current comparison
operators.

This proposal addresses:
    if CS1 and CS2 and Addr eq X"AA" then ... -- previously ok

    SEL <= CS1 and CS2 and Addr eq X"AA" ; -- previously ok

    SEL <= Addr eq X"AA" ; -- now ok

Still cannot do the following:
    -- BoolSel <= CS1 and CS2 and Addr eq X"AA" ; -- error result is std_ulogic

--------------------------------------------------------
Proposal 2:
Instead of the current proposal and the above addition,
do the following for boolean equivalence:

   As an expression is being evaluated, promote boolean
   to bit and boolean to std_ulogic as needed. Optionally
   extend this to include bit to std_ulogic.

   When an expression is being assigned
   or has reached a conditional demote the expression
   value as needed. From std_ulogic to boolean and
   bit to boolean as needed. Optionally extend this to
   include std_ulogic to bit.

If we can make this work, then we can keep our current
comparison operators (which I like better than proposal 1).

If we keep the current proposal (FT18), will it prevent us
from broadening it as in proposal 2?

--------------------------------------------------------

 From my perspective, the types boolean, bit, and std_ulogic
all carry the same designer intent, so why not make it
easier and more flexible to move between them.

Cheers,
Jim

-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training             mailto:Jim@SynthWorks.com
SynthWorks Design Inc.           http://www.SynthWorks.com
1-503-590-4787
Expert VHDL Training for Hardware Design and Verification
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