Hi,
FT10B: Conditional and Selected assignemnt for signals
and variables in a sequential context has been updated.
In the vhdl-200x-ft meeting on 8/16/2004, the following
issues were identified.
1) Fix line 110+
Line 110 is incorrect, Guarded is an option, not part of the
waveform. Statement needs be changed to "It is an error if the reserved work
guarded appears as an option in the sequential form of the signal assignment"
Resolution:
Too much typing, cutting, and pasting, and too little thinking.
Fixed as noted above.
2) Make Grammar left recursive:
conditional_waveforms ::=
{ waveform when condition else }
waveform when condition [ else waveform ]
Resolution: Changed
3) Do we want the ability not to have to have an assignment value?
Assignment of a value unconditionally is now done by simple
signal assignment. It was separated out so that the tranformations
that convert conditional and selected assignment have a name
to refer to simple signal assignment by (previously it was
defined in terms of sequential signal assignment which only
allowed what is now simple signal assignment).
Resolution: No Action required.
4) We should have NOTE specified in line 185.
Line 185 was editing notes and not ment to be part of the
document. It read: "Do we need something explaining how
the lack of a final else implies an assignment to unaffected?
This would mean changing the transformation to show to end
in else."
Resolution:
Transformation really should show else condition. It
was left out as it is not in 1076-2002, however, this may
have been an oversight.
Re-wrote the transformation so that it shows the else
condition. Explained that if there is no else condition
it is equivalent to having an else condition with
an assignment of unaffected.
I will schedule this for rereview at one of the future
VHDL-200X-FT meetings.
Regards,
Jim
-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Director of Training mailto:Jim@SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787 Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~Received on Tue Sep 21 12:17:54 2004
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