Subject: RE: [vhdl-200x-ft] Call for Vote on FT1
From: Peter Ashenden (peter@ashenden.com.au)
Date: Thu Jul 10 2003 - 09:17:12 PDT
Folks,
I would like to question why overloaded relational operators are being
defined in numeric_std for std_logic_vector. The proposal suggests that the
overloaded operators would provide numeric comparisons.
But the numeric_std package already provides comparison operators for
unsigned and signed parameters, interpreting the parameters as binary-coded
integers. Std_logic_vector values don't necessarily represent binary-coded
integers, so defining an operator that assumes that interpretation seems out
of order.
We deliberately define unsigned and signed to specify numeric
interpretation. Extending the interpretation to std_logic_vector appears to
me to be breaking the safety that the strong type system affords. A
designer should use unsigned or signed if they intend numeric interpretation
and std_logic_vector otherwise. Where a std_logic_vector needs to be
reinterpreted as representing a number, an explicit type conversion should
be used to document the fact.
If the 1076.3 WG wants to overload "<" for std_logic_vector in numeric_std,
do they also want to overload it for bit_vector in numeric_bit? If so, I
would object to that for the same reasons.
Cheers,
PA
-- Dr. Peter J. Ashenden peter@ashenden.com.au Ashenden Designs Pty. Ltd. www.ashenden.com.au PO Box 640 Ph: +61 8 8339 7532 Stirling, SA 5152 Fax: +61 8 8339 2616 Australia Mobile: +61 414 70 9106> -----Original Message----- > From: owner-vhdl-200x-ft@eda.org > [mailto:owner-vhdl-200x-ft@eda.org] On Behalf Of Jim Lewis > Sent: Saturday, 5 July 2003 12:35 > To: vhdl-200x-ft@eda.org > Subject: [vhdl-200x-ft] Call for Vote on FT1 > > > Dear colleagues, > > I'd like to call for a vote on change proposal > FT1: Allow explicit operators (ie: ">") overload implicit operators > > The summary and detailed change proposal for FT1 can be found > at http://www.eda-twiki.org/vhdl-200x/vhdl-200x-ft/proposals > > For the proposal, you can > (1) vote to accept the analysis and any changes it proposes, or > (2) vote to reject the analysis, citing reasons and revisions to make > the analysis acceptable > (3) abstain > > If you change your mind during the vote period, I will count the last > vote received from you. I will acknowledge votes by reply email. > > Please note that only current DASC members are eligible to have their > vote recognized. For this ballot, I will also collect votes from > non-DASC-members and tally them separately for information. > > Please forward your vote to me at jim@synthworks.com by 5:00pm US-PST > Friday 25 July 2003. Please also indicate whether you are a DASC > member. (If you want to join up, see www.dasc.org for details.) > > Thanks for your participation! > > Cheers, > > Jim Lewis > VHDL-200X-FT Co-leader > > -- > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > ~~~~~~~~~ > Jim Lewis > Director of Training mailto:Jim@SynthWorks.com > SynthWorks Design Inc. http://www.SynthWorks.com > 1-503-590-4787 > > Expert VHDL Training for Hardware Design and Verification > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > ~~~~~~~~~ >
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