Subject: Re: [vhdl-200x-ft] Call for Vote on FT1
From: Jim Lewis (Jim@SynthWorks.com)
Date: Fri Jul 11 2003 - 07:11:20 PDT
Peter,
It was decided by 1076.3 working group to create a package
in the spirit of std_logic_unsigned for numeric_std.
This package will create a full complement of arithmetic
operators for std_logic_1164 (mostly the same overloading
that is provided by numeric_std except for those that
overlap with other packages). There was much discussion of
the issues there and why people want it.
FT1 simply makes it legal for the 1076.3 working group to
overload the comparison operators as well as the other
operators.
The impact to vendors is minimal as they already handle
this for std_logic_unsigned. In fact it may end up being
a simplification as they can take off their switches that
allow the user to break the current interpretation of the
language that disallows this.
Liking or not liking std_logic_unsigned/numeric_std_unsigned
should not impact this proposal as this one simply
cleans up the overloading rules between implicit operators
and explicit operators.
In addition, having the unsigned arithmetic operators in
a package separate from std_logic_1164 permits greater
flexability in the usage model. If you feel that std_logic_vector
should not be used for arithmetic, do not include the
package that overloads it.
Regards,
Jim
Peter Ashenden wrote:
> Folks,
>
> I would like to question why overloaded relational operators are being
> defined in numeric_std for std_logic_vector. The proposal suggests that the
> overloaded operators would provide numeric comparisons.
>
> But the numeric_std package already provides comparison operators for
> unsigned and signed parameters, interpreting the parameters as binary-coded
> integers. Std_logic_vector values don't necessarily represent binary-coded
> integers, so defining an operator that assumes that interpretation seems out
> of order.
>
> We deliberately define unsigned and signed to specify numeric
> interpretation. Extending the interpretation to std_logic_vector appears to
> me to be breaking the safety that the strong type system affords. A
> designer should use unsigned or signed if they intend numeric interpretation
> and std_logic_vector otherwise. Where a std_logic_vector needs to be
> reinterpreted as representing a number, an explicit type conversion should
> be used to document the fact.
>
> If the 1076.3 WG wants to overload "<" for std_logic_vector in numeric_std,
> do they also want to overload it for bit_vector in numeric_bit? If so, I
> would object to that for the same reasons.
>
> Cheers,
>
> PA
>
> --
> Dr. Peter J. Ashenden peter@ashenden.com.au
> Ashenden Designs Pty. Ltd. www.ashenden.com.au
> PO Box 640 Ph: +61 8 8339 7532
> Stirling, SA 5152 Fax: +61 8 8339 2616
> Australia Mobile: +61 414 70 9106
>
>
>
>>-----Original Message-----
>>From: owner-vhdl-200x-ft@eda.org
>>[mailto:owner-vhdl-200x-ft@eda.org] On Behalf Of Jim Lewis
>>Sent: Saturday, 5 July 2003 12:35
>>To: vhdl-200x-ft@eda.org
>>Subject: [vhdl-200x-ft] Call for Vote on FT1
>>
>>
>>Dear colleagues,
>>
>>I'd like to call for a vote on change proposal
>>FT1: Allow explicit operators (ie: ">") overload implicit operators
>>
>>The summary and detailed change proposal for FT1 can be found
>>at http://www.eda-twiki.org/vhdl-200x/vhdl-200x-ft/proposals
>>
>>For the proposal, you can
>>(1) vote to accept the analysis and any changes it proposes, or
>>(2) vote to reject the analysis, citing reasons and revisions to make
>> the analysis acceptable
>>(3) abstain
>>
>>If you change your mind during the vote period, I will count the last
>>vote received from you. I will acknowledge votes by reply email.
>>
>>Please note that only current DASC members are eligible to have their
>>vote recognized. For this ballot, I will also collect votes from
>>non-DASC-members and tally them separately for information.
>>
>>Please forward your vote to me at jim@synthworks.com by 5:00pm US-PST
>>Friday 25 July 2003. Please also indicate whether you are a DASC
>>member. (If you want to join up, see www.dasc.org for details.)
>>
>>Thanks for your participation!
>>
>>Cheers,
>>
>>Jim Lewis
>>VHDL-200X-FT Co-leader
>>
>>--
>>~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>>~~~~~~~~~
>>Jim Lewis
>>Director of Training mailto:Jim@SynthWorks.com
>>SynthWorks Design Inc. http://www.SynthWorks.com
>>1-503-590-4787
>>
>>Expert VHDL Training for Hardware Design and Verification
>>~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>>~~~~~~~~~
>>
>
>
>
>
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