Hi Martin,
Thank you for your feedback. I was in meetings all day today so I couldn't respond earlier.
This page is an exploration of ideas of supporting a capability to bundle ports based on requirements the WG has collected. Any syntax is preliminary and should be used with great caution. The specific purpose of the page is to introduce an approach that can grow beyond just signals and to contrast it with that based on signals of a record type with each element of the record having potentially a different mode. I foresee many definitional issues trying to merge the concepts of mode and type, which is the reason I am pursuing this alternate approach that leaves objects alone. But as you, and also Ryan, observed, it creates other issues. I believe that we can get closer to a solid solution only by working out the semantics of the necessary concepts cleanly, making them fit the language architecture and philosophy, and then defining syntax supporting the semantics.
Regarding the example, your concern about where the selection ought to be made has been brought forth by others as well. As it stands, I believe that the example is a boundary case that illustrates certain issues, and any solution should support it. The specific VHDL files intend to parallel those of Brent's original use case closely while demonstrating the bundle/interface/port view approach. This is also why the aliases are done as they are, but as you suggest aliases could be defined differently.
Ernst
On Mon, 16 Nov 2015 08:46:07 +0000, Martin.J Thompson <Martin.J.Thompson@zf.com> wrote:
(Originally sent just after the last telecon, but my email address has changed since I signed up to the reflector, hence a slight delay. Thanks to Jim for working through this with me!)
Hi all,
Thanks Jim for making the meeting recording available - that will enable me to keep up with the discussions as well as just reading the Wiki pages - hopefully I can make some constructive comments again :)
With regard to the duplication of elements when creating a port view (for defining visibility): Although it does seem verbose, it also feels (to me) very VHDL-like. The verboseness is not as big an issue as it might seem (to my mind) as it is only a "one-off" piece of code when defining an interface for use, so the "end-user" of an interface will only have to "make use" of these definitions. For example, I recently did a system full of AXI and AXI-Stream interfaces - I would only have needed each of those interfaces creating in a package once at the start of the project, and then I could have gained enormous amounts of readability and code-size reduction, even if those packages were a bit big. And with standard buses like that, I probably wouldn't have even had to write them myself :)
A more critical issue (it seems to me) is that the user of the interface (in an entity) gets verboseness in the use of many dotted-relationships (and the use of aliases to make it more tractable)..
Looking at the example of the "slave_ent" from Ernst's proposal would it also be possible to do this:
---
alias mst is cpu_bus_rif.master_rl;
alias slv is cpu_bus_rif.slave_rl;
---
and then refer to "mst.addr_vl", "slv.data_vl"?
This might be a useful halfway-house?
Another thought which occurs to me looking at that example: the passing of the slave ID to the slave "feels wrong" - the mapping/wiring to specific slaves should be done in the higher-level instance. The slave should be unaware of its "location" in the system. But maybe that's a point of opinion rather than technical!
Cheers,
Martin
--
Martin Thompson BEng(Hons) MIET CEng
Technical Specialist - embedded systems
Conekt
ZF TRW Technical Centre, Stratford Road, Solihull, B90 4GW, UK
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Received on Wed Nov 18 21:28:36 2015