I tried to send this a week ago, but the eda.org mail server wouldn't accept it. Hopefully it will work if I try it again. I'm sorry I missed the telecon again last Thursday. I've looked over a good bit of the examples, and what I see concerns me. It looks like we're entangling the type system with port modes. The previous proposal I liked best had user-defined "directions" besides just in,out,inout and the other ones nobody uses. As much as possible, I think it's good to keep the direction and type orthogonal. The examples I've seen create a "view" or similar that is a conflation of data type and direction. Possibly this is the best solution, but the time I've had to spend on it leaves me nervous. There are several other aspects of VHDL that I wish we had crafted to be more orthogonal. Take protected types, for example. Here we mix data types with object class (shared variable). And now we have several proposals to try to fix up the loose ends: arrays of protected types, protected types to/from entities, etc. I know you guys are working hard to make the new feature good. I'll try to steal some time away from other projects to participate more. Thanks! - Ryan --- Ryan Hinton L-3 Communication Systems / Communication Systems West ryan.w.hinton@L-3com.comReceived on Wed Nov 18 13:18:19 2015
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