RE: [vhdl-200x] Heterogeneous Interfaces in VHDL

Hi Peter,

 

You are quite right in pointing out the lack of detail related to import and
export. The reason for the omission is in part that in previous discussions
the WG had suggested to first focus on the bundling capabilities of
interfaces. As a result, the document just mentions the subject of
import/export without much depth, but I agree that this has to be
back-filled. Can I pick your brain when I get there to build an
understanding of the finer points of this capability?

 

Regards.

Ernst

 

From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] On Behalf Of
Peter Flake
Sent: Thursday, June 25, 2015 9:39 PM
To: vhdl-200x@eda.org
Subject: RE: [vhdl-200x] Heterogeneous Interfaces in VHDL

 

Hi Ernst,

 

Thanks for your overview of SystemVerilog interfaces.  One point that is
missing is that the import/export feature is aimed at transaction level
modelling, like in SystemC.  This feature allows a call in one module
instance to a task in another module instance without the caller knowing the
path name of the callee.  The task operates on local module data, so cannot
be located in a package.  A point of clarification is that a virtual
interface is essentially a pointer to an interface instance.

 

One problem that we need to be careful about is the use case where the
interface is defined by one vendor and various IP blocks are defined by
other vendors.  This needs a relaxation of the type system, like the
situation we already have with records.

 

Regards,

 

Peter.

 

 

From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] On Behalf Of
Ernst Christen
Sent: 10 June 2015 07:07
To: Brent Hayhoe; vhdl-200x@eda.org
Subject: Re: [vhdl-200x] Heterogeneous Interfaces in VHDL

 

I have updated the document that Brent created with my notes from the last
meeting, and I have added a new page at
http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/SVInterfaces that gives an
overview of the bundling capabilities of SV interfaces. I'll add the
behavioral aspects as well once I have familiarized myself with them.

 

Regards.

Ernst
 

On Wed, 03 Jun 2015 17:19:18 +0100, Brent Hayhoe <Brent.Hayhoe@Aftonroy.com>
wrote:

 

 Following the meetings discussing interfaces and Ernst's excellent white
paper 
 detailing initial requirements, I've set up some 'whiteboard' pages in
order to 
 provide a brainstorming mechanism for the group.

If you can't get to the meetings then please add your suggestions, comments
and 
 questions on these pages. The idea is to keep it free-form bullet points
and/or 
 examples.

These will be reviewed via the WG meetings.

I've set up three pages initially:

 
http://www.eda-twiki.org/cgi-bin/view.cgi/P107/HeterogeneousInterfaceRequirement
s

This contains the requirements as detailed in Ernst's white paper.
    Ernst, can you update this with the modifications we made at the last
    meeting?



    http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/InterfaceConcepts

This is some bullet points and examples I put together regarding new mode 
 requirements for a simple CPU master/slave interface.



    http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/InterfaceBundles

Some bullet points on the new 'bundle' requirements for interfaces. This is
the 
 first priority for the next meeting.


These areas can all be accessed from a new 'Whiteboards' link on the main
P1076 
 web page.

The aim is for the WG meeting to condense these concepts and requirements
into a 
 final proposal(s).


Regards,

Brent.


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