I (and my team) would be very interested in the interfaces and directionality definitions as mentioned in previous ideas like http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/InterfaceAttributes. I work on a what is effectively a transpiler that generates VHDL from various high-level languages. The VHDL we generate is very complicated and we have to jump through hoops to turn dataflow-esque form into a process-oriented implementation that has many complicated record types flowing between components. Our compiler must decompose these high-level, nested "record" types into parallel input and output paths that make the VHDL (and therefore debugging waveforms, etc.) quite ugly. Given the proposals such as the one above our compiler could keep these structures intact and emit varying flavors of them for the directionality of the connections. This should be a win-win all around. Cheers! Dustyn Blasig National Instruments From: Daniel Kho <daniel.kho@gmail.com> To: "vhdl-200x@eda.org" <vhdl-200x@eda.org>, Date: 04/28/2015 03:24 AM Subject: Re: [vhdl-200x] A Challenge Sent by: owner-vhdl-200x@eda.org I will really like to see at least one of the proposals on block interfaces get through to the next revision. I'm particularly interested in John's conjugated ports proposal: http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/InterfaceAttributes Cheers, Dan On 28 April 2015 at 14:43, Srinivasan Venkataramanan <svenka3@gmail.com> wrote: I second Radek on DPI. Will be glad to assist in any possible way in this feature if needed On 28-Apr-2015 12:11 pm, "Radosław Nawrot" <Radoslaw.Nawrot@aldec.com.pl> wrote: Hi Jim, Hi All I don't know if this appeal concerns features that are not in wiki proposals or not on the voting list. I assume that If It's not on voting list - it was not considered to work on it. IMHO very important feature would be DPI for VHDL: http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/DpiProposal Even in basic variation of proposal (only DPI_C) i would be usefull and gives user many new opportunities (simple and fast access to golden model, Xtors, own library or different tool), Best Regards, Radek -----Original Message----- From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] On Behalf Of Jim Lewis Sent: Monday, April 27, 2015 7:21 PM To: vhdl-200x@eda.org Subject: [vhdl-200x] A Challenge Hi, Our current PAR expires at the end of 2015. I have applied for an extension, which we should be able to get. OTOH, if we could consider getting a set of work done and balloted by then. What I would like you to do then is look over the proposals. Are there one to three that would really make a difference in your work, that are minimal risk of unintended side effects, and that you would perhaps be willing to help work on the LCS for? Please reply to this with your list and why you need the item. We can talk about it in the meeting on Thursday. Best Regards, Jim -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Jim@SynthWorks.com VHDL Training Expert http://www.SynthWorks.com IEEE VHDL Working Group Chair OSVVM, Chief Architect and Cofounder 1-503-590-4787 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Wed Apr 29 12:31:07 2015
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