Interfaces would be top of my list - save on passing two records around, or worse, just pasting long lists of signals (vendor AXI cores are particularly painful). I can see DPI being very helpful also... Not sure if they fall into the "minimal risk" category though! Arbitrary integer lengths would also be of use, although less than interfaces Sorry, won't be able to join on Thursday. Cheers, Martin > -----Original Message----- > From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] On > Behalf Of Jim Lewis > Sent: 27 April 2015 18:21 > To: vhdl-200x@eda.org > Subject: [vhdl-200x] A Challenge > > Hi, > Our current PAR expires at the end of 2015. I have applied for an > extension, which we should be able to get. > > OTOH, if we could consider getting a set of work done and balloted by > then. What I would like you to do then is look over the proposals. > Are there one to three that would really make a difference > in your work, that are minimal risk of unintended side effects, and > that you would perhaps be willing to help work on the LCS for? > > Please reply to this with your list and why you need the item. We can > talk about it in the meeting on Thursday. > > Best Regards, > Jim > > -- > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > Jim Lewis Jim@SynthWorks.com > VHDL Training Expert http://www.SynthWorks.com > IEEE VHDL Working Group Chair > OSVVM, Chief Architect and Cofounder > 1-503-590-4787 > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > > -- > This message has been scanned for viruses and > dangerous content by MailScanner, and is > believed to be clean. > -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Tue Apr 28 04:44:47 2015
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