> Hi Tristan, > Yes I can see that now. How dense of me. OTOH, the lack of basic > introspection of single dimensional array aggregates is annoying. Yes, aggregate rules aren't very intuitive! Tristan. > OTOH, there was a significant change to array aggregates in > VHDL-2008. Basically, they now support concatenation when the > target is an array type. As a result, even if we add introspection > to > recognize single dimensional array aggregates, this one is still > going to be ambiguous with std_ulogic_vector. > > Thanks for straightening me out on this. > > Jim -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Mon Apr 13 08:22:03 2015
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