Hi Tristan, Yes I can see that now. How dense of me. OTOH, the lack of basic introspection of single dimensional array aggregates is annoying. OTOH, there was a significant change to array aggregates in VHDL-2008. Basically, they now support concatenation when the target is an array type. As a result, even if we add introspection to recognize single dimensional array aggregates, this one is still going to be ambiguous with std_ulogic_vector. Thanks for straightening me out on this. Jim On 4/10/2015 11:28 PM, Tristan Gingold wrote: > On 10/04/15 22:24, Jim Lewis wrote: >> Hi Tristan, >> Here are a few more details, the following are defined in a package. >> For the whole package, see: >> http://www.synthworks.com/downloads/AggregateIssuePkg.vhd > > [...] > >> In the second function, the return statement: >> return to_string( (Data, ErrorMode) ) ; >> >> With VHDL-2008 is now ambiguous since "(Data, ErrorMode)" can be >> interpreted as a record, of a type such as UartStimType, or it can be >> interpreted as a single std_logic_vector. > > No, almost nothing has changed since 87. Even in VHDL-87 (if there > were a to_string [slv return string] function), this would have > been ambiguous because the type of an aggregate is determined by > the context, not by the aggregate itself. So even VHDL-87 ight > consider (Data, ErrorMode) as single std_logic_vector (but will > then report an error on the elements). > > Regards, > Tristan. > > -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Jim@SynthWorks.com VHDL Training Expert http://www.SynthWorks.com IEEE VHDL Working Group Chair OSVVM, Chief Architect and Cofounder 1-503-590-4787 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Sat Apr 11 08:37:09 2015
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