RE: [vhdl-200x] Interfaces with normal, conjugated and monitor flavours

Hi Brent,

I agree it is concise, but why do we need the interface statement?  Is there
anything else that can go in it apart from ports?

If not, we can just define the ports on their own:

port cpu_bus_master of r_cpu_bus is
       adr: out;
       dat: inout;
       cs:  out;
       we:  out;
       en:  out;
       ack: in;
       err: in;
end port
port cpu_bus_slave of r_cpu_bus is
       adr: in;
       dat: inout;
       cs:  in;
       we:  in;
       en:  in;
       ack: out;
       err: out
end port

And use them without a dot:

entity cpu_master is
    port(
       rst:     in std_logic;
       clk:     in std_logic;
       cpu_bus: i_cpu_bus_master
    );
end entity cpu_master;

Regards,

Peter.

-----Original Message-----
From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] On Behalf Of
Brent Hayhoe
Sent: 03 March 2015 23:33
To: vhdl-200x@eda.org
Subject: Re: [vhdl-200x] Interfaces with normal, conjugated and monitor
flavours


 From your interface suggestions, I thought that I'd detail and adapt them
to a possible solution.

It looks quite concise and a nice first attempt.

What do you think?

So the record and signals:-

    type r_cpu_bus is record
       adr:  std_logic_vector(15 downto 0);  -- Address
       dat:  std_logic_vector(15 downto 0);  -- Data between master and
slave
       cs:   std_logic_vector(7 downto 0);   -- ChipSelect-bus from master
       we:   std_logic;                      -- Write enable from master
       en:   std_logic;                      -- Enable from master
       ack:  std_logic;                      -- Acknowledge from slave
       err:  std_logic;                      -- Error from slave
    end record r_cpu_bus;

    signal s_rst:     std_logic;
    signal s_clk:     std_logic;
    signal s_cpu_bus: r_cpu_bus;



The interface definition to associate the modes for master and slave ports
with the record type.

I've included the short attribute option (defining the slave port) as a
comment with an attribute of converse/conjugate/inverse/opposite etc, at the
end:-

interface i_cpu_bus of r_cpu_bus is
    port master(
       adr: out;
       dat: inout;
       cs:  out;
       we:  out;
       en:  out;
       ack: in;
       err: in
    );
    port slave(
       adr: in;
       dat: inout;
       cs:  in;
       we:  in;
       en:  in;
       ack: out;
       err: out
    );
--   port slave(master'converse);
end interface i_cpu_bus;



This is how they would be used to encapsulate the mode and type together in
an entity declarations:-

entity cpu_master is
    port(
       rst:     in std_logic;
       clk:     in std_logic;
       cpu_bus: i_cpu_bus.master
    );
end entity cpu_master;

entity cpu_slave is
    port(
       rst:     in std_logic;
       clk:     in std_logic;
       cpu_bus: i_cpu_bus.slave
    );
end entity cpu_slave;



And finally the normal record use when instantiating components:-

cpu_master_inst: cpu_master
    port map(
       rst      => s_rst,
       clk      => s_clk,
       cpu_bus  => s_cpu_bus
    );

cpu_slave_inst: cpu_slave
    port map(
       rst      => s_rst,
       clk      => s_clk,
       cpu_bus  => s_cpu_bus
    );




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