Re: [vhdl-200x] Interfaces with normal, conjugated and monitor flavours

On 04/03/15 00:32, Brent Hayhoe wrote:
>
>  From your interface suggestions, I thought that I'd detail and adapt
> them to a possible solution.
>
> It looks quite concise and a nice first attempt.
>
> What do you think?
>
> So the record and signals:-
>
>     type r_cpu_bus is record
>        adr:  std_logic_vector(15 downto 0);  -- Address
>        dat:  std_logic_vector(15 downto 0);  -- Data between master and
> slave
>        cs:   std_logic_vector(7 downto 0);   -- ChipSelect-bus from master
>        we:   std_logic;                      -- Write enable from master
>        en:   std_logic;                      -- Enable from master
>        ack:  std_logic;                      -- Acknowledge from slave
>        err:  std_logic;                      -- Error from slave
>     end record r_cpu_bus;
>
>     signal s_rst:     std_logic;
>     signal s_clk:     std_logic;
>     signal s_cpu_bus: r_cpu_bus;
>
>
>
> The interface definition to associate the modes for master and slave
> ports with the record type.
>
> I've included the short attribute option (defining the slave port) as a
> comment
> with an attribute of converse/conjugate/inverse/opposite etc, at the end:-
>
> interface i_cpu_bus of r_cpu_bus is
>     port master(
>        adr: out;
>        dat: inout;
>        cs:  out;
>        we:  out;
>        en:  out;
>        ack: in;
>        err: in
>     );
>     port slave(
>        adr: in;
>        dat: inout;
>        cs:  in;
>        we:  in;
>        en:  in;
>        ack: out;
>        err: out
>     );
> --   port slave(master'converse);
> end interface i_cpu_bus;
>
>
>
> This is how they would be used to encapsulate the mode and type together
> in an
> entity declarations:-
>
> entity cpu_master is
>     port(
>        rst:     in std_logic;
>        clk:     in std_logic;
>        cpu_bus: i_cpu_bus.master
>     );
> end entity cpu_master;
>
> entity cpu_slave is
>     port(
>        rst:     in std_logic;
>        clk:     in std_logic;
>        cpu_bus: i_cpu_bus.slave
>     );
> end entity cpu_slave;
>
>
>
> And finally the normal record use when instantiating components:-
>
> cpu_master_inst: cpu_master
>     port map(
>        rst      => s_rst,
>        clk      => s_clk,
>        cpu_bus  => s_cpu_bus
>     );
>
> cpu_slave_inst: cpu_slave
>     port map(
>        rst      => s_rst,
>        clk      => s_clk,
>        cpu_bus  => s_cpu_bus
>     );

 From a language point of view, this looks fine.

My concern is from a user point of view: this is more verbose than the
initial proposal: you need to declare a record and then an interface.
I think this is a critical point, but I'd like to heard from others on
that point.

Tristan.


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