Re: AW: [vhdl-200x] Interfaces with normal, conjugated and monitor flavours

> > Let's propose:
> >        bus : interface i_cpu_bus'conjugated; or
> >        bus : i_cpu_bus'conjugated;
> >(I am not a native English speaker, but there might be a better
> >  word than conjugated.  Maybe reverse ?)
> 
> The attribute syntax looks cleaner.
> If you spare the interface keyword, can it conflict with the default
> direction of ports?

Not really.  We know that i_cpu_bus is an interface, so having the
interface keyword before is simply redundant.


> Using 'reverse (or 'reverse_interface) is like using 'reverse_range
> on arrays.

What about 'opposite_mode / 'in_mode ?

> What about using the keyword bus instead of interface?
> Pros:
> - it's as short as in/out/inout in a port description
> - 'reverse_bus looks more like 'reverse_range than 'reverse_interface
> Cons:
> - maybe it's a widely used signal name

No, bus is already a reserved word in VHDL.  No possible conflict and
no extra reserved word.

> - interface is better known from OOP

Yes but this feature is not really about OOP, and an interface in
Java-like languages is not the same thing.  The advantage of 'interface'
keyword (argh, the right words are reserved identifier) is similarity
with systemverilog.  But I am not sure that this is so important.

> Additional attributes:
> Shout there be a possibility to extract all in or out signals by
> using the
> attribute syntax? This could help to connect new entities with
> interfaces
> to legacy entities with one record per direction.

Well, you can connect by association or write your interface using
two records.  Not sure it is worth an extra feature.

As a language designer, I far more prefer to add features slowly.  It is
so easy to get screwed.  But maybe I am too prudent.

Tristan.

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