On 30/01/2015, at 12:48 am, Jennings, Kevin <Kevin.Jennings@Burroughs.com> wrote: > By 'dynamically elaborated', do you mean they are not elaborated until the simulation is run? If so, this would seem to be an implementation issue of the simulator since VHDL doesn't have anything defined in the LRM that would allow for that. Can you give an example to clarify? 14.6 Dynamic elaboration The execution of certain constructs that involve sequential statements rather than concurrent statements also involves elaboration. Such elaboration occurs during the execution of the model. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Thu Jan 29 03:56:39 2015
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