RE: [vhdl-200x] Proposal for improved physical types

By 'dynamically elaborated', do you mean they are not elaborated until the simulation is run?  If so, this would seem to be an implementation issue of the simulator since VHDL doesn't have anything defined in the LRM that would allow for that.  Can you give an example to clarify?

Kevin Jennings
________________________________________
From: owner-vhdl-200x@eda.org [owner-vhdl-200x@eda.org] On Behalf Of tgingold@free.fr [tgingold@free.fr]
Sent: Thursday, January 29, 2015 3:05 AM
To: vhdl-200x@eda.org
Subject: Re: [vhdl-200x] Proposal for improved physical types

> Yes, that's the reason Jan and other proponents have proposed that
> integer types be constrained, but only at elaboration time, or as I
> put it, at a higher-level hierarchy of the design. Think of it
> similar to deferring the constraints to a later (or higher) phase of
> the design. At the block level, integer types can be unconstrained,
> but will be constrained later at the system level. So there is no
> concern of infinite precision arithmetic. At elaboration time,
> precision will still be constrained and finite.

Hard to achieve that for subprograms, which are dynamically elaborated.

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