Hi All, Heads up. The following paragraph is not ok. This sort of rhetoric can be construed to be vendor bashing. Please focus on the technical aspects of the discussion. > These sort of objections you cite sound like reps from the EDA industry complaining that they don't want to be forced to do "hard" things or make improvements to their legacy code due to the > expense. It wasn't that long ago that a certain major vendor barely supported any more than the subset of VHDL that mapped 1-to-1 with Verilog. Should the language have been frozen then? I am not pointing a finger at just Kevin. We all need to be mindful. Jim -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Jim@SynthWorks.com VHDL Training Expert http://www.SynthWorks.com IEEE VHDL Working Group Chair OSVVM, Chief Architect and Cofounder 1-503-590-4787 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Wed Jan 28 15:09:19 2015
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