RE: [vhdl-200x] Volunteers for Chairing 1076.4 (VITAL) or 1076.6 (RTL Synthesis)

The "Timing Working Group" (TWG) created the VITAL (VHDL Initiative Towards Asic Libraries) in response to the choppy and uneven nature used to express gate-level designs in VHDL.  It seemed everyone had their own way to do it.  That standard, 1076.4, has remained a separate document from the main 1076 standard.  

With that information, and do that extent, I wondered if it was time to join them into one.

-Dennis

-----Original Message-----
From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] On Behalf Of Steve Grout
Sent: Wednesday, January 28, 2015 2:04 PM
To: vhdl-200x@eda.org
Subject: Re: [vhdl-200x] Volunteers for Chairing 1076.4 (VITAL) or 1076.6 (RTL Synthesis)

When did VHDL not include gate level elements?
--Steve Grout


On 1/28/2015 2:41 PM, Tristan Gingold wrote:
> On 27/01/15 00:35, Brophy, Dennis wrote:
>> Jim,
>>
>>    Why not roll the gate-level elements of 1076.4 into 1076 itself?
>> Verilog has the gate-level elements as a part of 1800.
>
> Do we really want to make the VHDL standard as fat as the 
> SystemVerilog one ?
>
> Tristan.
>
>

--
This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.



-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.