Hi, It is time to rank each of the requirements that is on the proposals page. I have put an Excel spreadsheet for ranking at: http://www.eda-twiki.org/twiki/pub/P1076/CollectedRequirements/vhdl_requirements_priority.xlsx Please give proposals a value between 0 and 10. Where 0 is a low rank and 10 is a high rank. Please rank them based on value, usefulness, and fit into the language. Please put comments on the TWIKI page of the proposal. Email to me a copy of your ranking sheet when you have completed it. Particularly want to know which features you would be using frequently today if they were already implemented. Everyone is welcome to rank proposals. Membership in the working group is based on participating through voting on items such as this one. I realize each of the proposals is in different state of completeness. That is ok as we are not ranking the proposals on completeness. Some of the proposals have divergent and/or competing ideas in them. If you do have a preference, make sure to comment on the TWIKI page. Best Regards, Jim -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis VHDL Training Expert, SynthWorks IEEE 1076 VHDL Working Group Chair Open Source VHDL Verification Methodology (OSVVM), Chief Architect and Co-founder 1-503-590-4787 Jim@SynthWorks.com http://www.SynthWorks.com VHDL Training on leading-edge, best coding practices for hardware design and verification. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Thu Nov 13 13:39:29 2014
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