Hello, Trying to empty my "to reply" list... Le 2014-10-27 02:38, Jones, Andy D a écrit : >>> Here we have i4 + i4. As long as the + integer operator does not >>> overflow, the result can be correctly reduced to mod4 during >>> assignation. > >> Sorry, but not. The above code is valid VHDL, and will produce an >> error >> during simulation if overflow occurs. I don't think we want to change >> the >> semantic of existing VHDL design. > > I believe the point was that the overflow does not occur in "+", but > in the assignment to another i4. If it had been assigned to an i8, > then there would be no overflow. there is another point I have not seen mde (and not directly related to Andy's post) : even when using vanilla integer, the "+" operator must know when it overflows because the result must be arithmetically valid. So there is already a built-in capability to handle this, which can be tuned to different values to restrict the range for example. That's what I'd like to reuse. > The "+" operator only knows the type (integer) of the operands and > result. It does not know the subtypes. That's a grey area for me, an interesting point too. Too much implementation-dependent but I don't know the language. yg -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Fri Oct 31 04:07:07 2014
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