On 9 Aug 2014, at 1:42 am, Jim@synthworks.com wrote: > Has anyone tested the performance of bit_vector? I've looked through the source code of three VHDL and two Verilog implementations and found none of them had any bit packed vectors. They all treated them as purely arrays of objects other than for purposes of waveform dump files. It's not surprising there is no better performance than std_logic_vector. I did a literature search and could find no indication anyone has done so. There's nothing prohibiting packing bits for arrays. There's just no evidence lying around anyone tried to do native rate arithmetic on them in the observable past. If there had it would have had a disruptive influence that would likely have been noticed. I'd agree packed bit vectors are likely an evolutionary dead end. If you compare the effort to the incremental effort to implement Ada style modular integers modular integers would win. The point was not that bit vectors should be 'fixed', more that performance is not a goal to which to tool vendors have been aspiring and it's not a goal in the language definition either. I'd also suggest you're unwise to count on native machine logical or shift operator performance on modular integers either. While performance would be vastly superior to manipulating arrays of objects implementation would more likely avoid redesign where possible. It's mostly just another integer type. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Fri Aug 8 21:36:29 2014
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