Le 2014-08-08 16:04, whygee@f-cpu.org a écrit : > http://ygdes.com/GHDL/int_bool/ <...> > The script and all the files are available, > so i could just re-run it. I found the runtimes (run twice to be sure) #integer : 0.16user 0.00system 0:00.17elapsed 92%CPU 0.16user 0.00system 0:00.18elapsed 92%CPU #integer_range : 0.16user 0.00system 0:00.18elapsed 92%CPU 0.16user 0.00system 0:00.17elapsed 95%CPU # bit_vector : 69.21user 0.18system 1:14.39elapsed 93%CPU 68.65user 0.16system 1:13.89elapsed 93%CPU # std_ulogic_vector : 66.63user 0.04system 1:09.03elapsed 96%CPU 67.64user 0.07system 1:10.75elapsed 95%CPU I like VHDL's powerful abstraction but I'm ok to make some efforts to cut simulation time to 1/400, as it spare synthesis/place/root/flash time to test in FPGA. I already hear some people pointing at GHDL's "poor implementation", or "lack of focus on performance" but IMHO it's not the real issue. GHDL follows GHDL. Most simulators do it. VHDL says "integers are platform's native words" so be it. VHDL says "std_logic_vector is an array of resolved multi-value bits" so GHDL implements an array of these. VHDL says "performance is the tool implementor's problem" and nobody cares. At least, the modulo type is a step in the right direction because it would be hard to botch its implementation (ahem). YG -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Fri Aug 8 07:24:38 2014
This archive was generated by hypermail 2.1.8 : Fri Aug 08 2014 - 07:25:08 PDT